synopsys-dc

EE577b-Course-Project

Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo

Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.

RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.

This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).

My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools

This project presents the complete RTL design, functional verification, and synthesis analysis of a 24-hour digital clock using Verilog HDL, following an end-to-end ASIC VLSI design flow.

Full RTL-to-GDSII implementation of a 32-bit RISC Processor. Features Physical Design (P&R), CTS, and Timing Closure using Synopsys DC & Cadence Innovus.

全國大學校院積體電路設計競賽 實作練習

Logic Synthesis QOR study, the best and worst case for hold and setup

5-stage pipelined RISC-V (RV32I subset) processor in SystemVerilog that runs compiled C through variable-latency memories over an OBI-style request/ready protocol. Full ASIC flow: Synopsys DC synthesis at 641 MHz and Cadence Innovus place & route on NanGate 45 nm, plus OpenRAM SSRAM integration.

APB based SPI master protocol

complete walkthrough of the vlsi design process for an equation Y = 4^X development to sta, using synopsys

Complete ASIC implementation of the OpenCores DES core using Cadence Genus, Innovus, and Synopsys PrimeTime, from RTL synthesis to GDSII.

Dockerized container for Synopsys Design Compiler (DC) that can run ANYWHERE.

Radix-4 Modified Booth multiplier with a hand-built Dadda tree and Bewick sign extension, in SystemVerilog. It is integrated as the mantissa multiplier of an IEEE 754 half-precision FPU, and five Synopsys DC strategies are compared (up to 473.9 MHz) on NanGate 45nm.

This is a basic pipelined RISC-V processor (RV32I) made without a clock (Asycnhronous).

TCL-based heuristic engine for Post-Synthesis Leakage Power Optimization using Synopsys Design Compiler. Implements a Slack-Aware Batch & Revert algorithm.

32-bit RISC-V processor implementing out-of-order execution, register renaming, and precise retirement in SystemVerilog.